VSD – Static Timing Analysis – I

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VLSI – Essential timing checks

VSD – Static Timing Analysis – I
VSD – Static Timing Analysis – I



Enroll to vlsi academy sta checks course from Kunal (Digital and Sign-off expert at VLSI System Design(VSD)) at $9,99 using €10 Udemy Coupon Code.

Static timing analysis comprises broadly for timing checks, constraints and library. Having all of them in a single course makes it bulky. So we decided to have it in 3 parts and this is part I – Essential timing checks. This course will give an eagle’s eye to every timing check that is being performed in current industries for sign-off. This will also introduce you to basic terminologies for timing, which are needed for advanced courses on STA.

Timing comes at every step of physical design flow, but in this course, we primarily focus on signoff timing i.e. looking into each and every corner of design for any timing violations

The course starts from very basic and gradually takes you to an advanced level at an intermediate pace. So no questions on you missing any details

Hope you enjoy learning this course in the same way we enjoyed making them.

Happy Learning !!

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